Compared to mechanical circuit breaker

DC solid-state circuit breaker (SSCB) composed of semiconductor devices has great advantage in response time. The Si/SiC cascode element consisting of low-voltage silicon metal-oxide-semiconductor field-effect transistor (Si MOSFET) and high-voltage silicon carbon junction field-effect transistor (SiC JFET) has excellent switching characteristics. The reliability of semiconductor power element has always been the focus of DC SSCB. The test of the unclamped inductive switching (UIS) is an important method to assess reliability of the semiconductor power element. In this paper

the avalanche performance of Si/SiC cascode element during the UIS period is analyzed by means of experiment and simulation. Firstly

the avalanche performance under different load currents is obtained by increasing the on-time of the element. The results show that with the increase of the on-time the Si/SiC cascade element shows an abnormal performance of the avalanche-voltage drop during the avalanche period. Then

UIS tests is performed through a discrete Si/SiC cascode element

finding that the abnormal performance originates from the turn-on of SiC JFET during avalanche period. Finally

the 3D electrical-thermal coupling simulation of the Si/Sic cascade element is performed. The results show that the temperature of aluminum metal layer and bonding wire of SiC JFET rises during the avalanche period

leading to the increase of the gate equivalent-resistance of SiC JFET

and ultimately resulting in the turn-on of SiC JFET during the avalanche period.