A synchronous control system is designed to observably raise the success rate of synthetic test of circuit breaker. First

a hardware circuit of the synchronous control system is designed. Second

considering the source current is approximately linear in the zero area

the current model is simplified

and a program for predicting current zero is coded. According to the test data

the error between actual trigger time and setting time of the voltage circuit is less than 50 μs

and the error between actual trigger time and setting time of the arc prolonging circuit is less than 40 μs. The errors meet the design requirements

and can ensure the equivalence of the synthetic test

thus the performance of the synchronous control system is verified.